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Nederlands Buitenlands   Alles  Titel  Auteur  ISBN        
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Steven H. Voldman

ESD - Design and Synthesis

€ 133.95

The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip.


Taal / Language : English

Inhoudsopgave:
About the Author

Preface

Acknowledgements

Chapter 1 ESD Design Synthesis Basics

1.1 ESD Design Synthesis and Architecture Flow
1.2 ESD Design - The Signal Path and Alternate Current Path
1.3 ESD Electrical Circuit and Schematic Architecture Concepts
1.4 Mapping Semiconductor Chips and ESD Design
1.5 ESD Chip Architecture and ESD Test Standards
1.6 ESD Testing
1.7 ESD Chip Architecture and Alternative Current Path
1.8 ESD Networks, Sequencing and Chip Architecture
1.9 Latchup-free ESD Networks
1.10 ESD Design Concepts - Buffering Inter-device
1.11 ESD Design Concepts - Ballasting Inter-device
1.12 ESD Design Concepts - Ballasting Intra-device
1.13 ESD Design Concepts - Distributed Load Techniques
1.14 ESD Design Concepts - Dummy Circuits
1.15 ESD Design Concepts - Power supply De-coupling
1.16 ESD Design Concepts - Feedback Loop De-coupling
1.17 ESD Layout and Floorplan Related Concepts
1.18 ESD Design Concepts - Analog Design
1.19 ESD Design Concepts - Wire Bonds
1.20 ESD Computer Aided Design
1.21 Summary and Closing Comments

Problems
References

2. Chapter 2 ESD Architecture and Floorplanning

2.1 ESD Design Floor plan
2.2 Peripheral I/O Design
2.3 Lumped ESD Power Clamp in Peripheral I/O Design Architecture
2.4 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/slave ESD Power Clamp System
2.5 Array I/O
2.6 ESD Architecture - Dummy Bus Architecture
2.7 Native Voltage Power Supply Architecture
2.8 Mixed Voltage Architecture
2.9 Mixed Signal Architecture
2.10 Mixed Signal Architecture - Digital and Analog CMOS
2.11 Mixed Signal Architecture - Digital, Analog and RF Architecture
2.12 Summary and Closing Comments

Problems
References

3 Chapter 3 ESD Power Grid Design and Synthesis

3.1 ESD Power Grid
3.2 Semiconductor Chip Impedance
3.3 Interconnect Failure and Dynamic On-Resistance
3.4 Interconnect Wire and Via Guidelines
3.5 ESD Power Grid Resistance
3.6 Power Grid Layout Design
3.7 ESD Specification Power Grid Considerations
3.8 Power Grid Design Synthesis - ESD Design Rule Checking (DRC) Methods
3.9 Summary and Closing Comments

Problems
References

4 Chapter 4 ESD Power Clamp Design and Synthesis

4.1 ESD Power Clamps
4.2 Design Synthesis of ESD Power Clamps
4.3 Design Synthesis of ESD Power Clamps - The ESD Power Clamp Shunting Element
4.4 ESD Power Clamp Issues
4.5 ESD Power Clamp Design - MOSFET Power Clamp
4.6 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps
4.7 Master/Slave ESD Power Clamp Systems
4.8 Summary and Closing Comments

Problems
References


Chapter 5 ESD Signal Pin Network Design and Synthesis

5.1 ESD Signal Pin Structures
5.2 ESD Signal Pin Structures - ESD and Bond Pad Layout
5.3 ESD Design Synthesis and Layout of MOSFETs
5.4 ESD Design Synthesis and Layout of Diodes
5.5 ESD Design Synthesis of Silicon Controlled Rectifiers (SCR)
5.6 ESD Design Synthesis and Layout of Resistors
5.7 ESD Design Synthesis of Inductors
5.8 Summary and Closing Comments

Problems
References


Chapter 6 Guard Ring Design and Synthesis

6.1 Guard Ring Design and Integration
6.2 Guard Ring Characterization
6.3 Semiconductor Chip Guard Ring Seal
6.4 I/O to Core Guard Rings
6.5 I/O to I/O Guard Rings
6.6 Within I/O Guard Rings
6.7 ESD Signal Pin Guard Rings
6.8 Library Element Guard Rings
6.9 Mixed Signal Guard Rings - Digital to Analog
6.10 Mixed Voltage Guard Rings - High Voltage to Low Voltage
6.11 Passive and Active Guard Rings
6.12 Trench Guard Rings
6.13 Through Silicon Via (TSV) Guard Rings
6.14 Guard Ring Design Rule Checking (DRC)
6.15 Guard Ring and Computer Aided Design (CAD) Methods
6.16 Summary and Closing Comments

Problems
References


Chapter 7 ESD Full Chip Design Integration and Architecture

7.1 Design Synthesis and Integration
7.2 Digital Design
7.3 Custom Design versus Standard Cell Design
7.4 Memory ESD Design
7.5 Microprocessor ESD Design
7.6 Application Specific Integrated Circuits (ASICs)
7.7 CMOS Image Processing Chip Design
7.8 Mixed Signal Architecture
7.9 Summary and Closing Comments

Problems
References


Index

Extra informatie: 
Hardback
290 pagina's
Januari 2011
672 gram
253 x 175 x 22 mm
Wiley-Blackwell us
Levertijd: 5 tot 11 werkdagen