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Lee, Weng Fook

Verilog Coding for Logic Synthesis

€ 168.95

Verilog is a Hardware Description Language (HDL) used to design and document electronic systems. Verilog HDL allows designers to virtually design systems without expending time or resources on physical models. It is the most widely used HDL with a user community of more than 50,000 active designers.


Taal / Language : English

Inhoudsopgave:
Table of Figures.

Table of Examples.

List of Tables.

Preface.

Acknowledgments.

Trademarks.

Introduction.

Asic Design Flow.

Verilog Coding.

Coding Style: Best Known Method for Synthesis.

Design Example of Programmable Timer.

Design Example of Programmable Logic Block for Peripheral Interface.
Extra informatie: 
Hardback
310 pagina's
Januari 2003
614 gram
242 x 166 x 28 mm
Wiley-Blackwell us

Levertijd: 5 tot 11 werkdagen