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Khan, Shoab Ahmed

Digital Design of Signal Processing Systems

A Practical Approach

€ 133.95

Digital Design of Signal Processing Systems discusses a spectrum of architectures and methods for effective implementation of algorithms in hardware (HW). Encompassing all fac


Taal / Language : English

Inhoudsopgave:
Preface

Acknowledgement

1. Introduction to Digital Design of Signal Processing Systems

1.1. Fueling the Innovation: Moore s Law

1.2. Digital Systems

1.3. Examples of Digital Systems

1.4. Example: The Backplane of a Router

1.5. Digital Design Process

1.6. Digital Design Competing Objectives

1.7. Synchronous Digital Hardware Systems

1.8. Design Strategies

1.9. References

2. Digital Design Using HDL

2.1. Introduction to Verilog

2.2. System Design Flow

2.3. Verilog HDL

2.4. Four Levels of Abstraction

2.5. Verification in HW Design

2.6. System Verilog

2.7. Exercise

2.8. References

3. System Design Flow and Fixed Point Arithmetic

3.1. System Design Flow

3.2. Representations and Numbers

3.3. Floating point Format

3.4. Qn.m Format for Fixed point Arithmetic

3.5. Floating Point to Fixed Point Conversion

3.6. Block Floating Point Format

3.7. Digital Filters Forms

3.8. Exercise

3.9. References

4. DSP System Representations and Mapping on Fully Dedicated Architecture

4.1. Introduction

4.2. Discrete Real Time System

4.3. Synchronous Digital Hardware Systems

4.4. Kahn Process Network (KPN)

4.5. Representation Methods of DSP systems

4.6. Performance Measures

4.7. Fully Dedicated Architecture

4.8. Pipelining in Fully Dedicated Architecture

4.9. Selecting Basic Building Blocks

4.10. DFG to HW Synthesis

4.11. Exercise

4.12. References

5. Design Options for Basic Building Blocks

5.1. Introduction

5.2. Embedded Processors and Arithmetic Units in FPGAs

5.3. Instantiation of Embedded Blocks

5.4. Basic Building Blocks

5.5. Adders

5.6. Barrel Shifter

5.7. Parallel Multiplier Architectures

5.8. Cary Save Adder (CSA) and Compressors

5.9. Compression Trees

5.10. 2 s Complement Signed Multiplier

5.11. Compression Trees for Multi Operand Addition

5.12. Algorithm Transformations for CSA

5.13. Exercise

5.14. References

6. Multiplierless Multiplication by Constants

6.1. Introduction

6.2. Canonic Sign Digit (CSD) Representation

6.3. Minimum Signed Digit Representation

6.4. Multiplication by Constant in Signal Processing Algorithm

6.5. Fully Dedicated Architecture for Direct Form FIR Filter

6.6. Transposed Direct Form FIR Filter

6.7. Complexity Reduction

6.8. Distributed Arithmetic

6.9. FFT Architecture using FIR Filter Structure

6.10. Exercise

6.11. References

7. Pipelining, Retiming, Look ahead Transformation and Polyphase Decomposition

7.1. Introduction

7.2. Pipelining and Retiming

7.3. Digital Design of Feedback Systems

7.4. C slow Retiming

7.5. Look Ahead Transformation for IIR filters

7.6. Polyphase Structure for Decimation and Interpolation Applications

7.7. Exercise

7.8. References

8. Unfolding and Folding Architectures

8.1. Introduction

8.2. Sampling Rate Considerations

8.3. Unfolding Techniques

8.4. Folding Techniques

8.5. Folding Regular Structured DFGs

8.6. Mathematical Transformation for Folding

8.7. Exercise

8.8. References

9. Finite State Machine based Design

9.1. Time Shared Architecture Design Examples

9.2. Sequencing and Control

9.3. Algorithm State Machine Representation

9.4. FSM Optimization for Low Power and Area

9.5. Design for Testability

9.6. Testing FSMs

9.7. Sequence Conformance

9.8. Coverage Metrics for Design Validation

9.9. Methods for Reducing Power of a State Machine

9.10. Exercise

9.11. References

10. Micro program State Machines

10.1. Introduction

10.2. Micro programmed Controller

10.3. Counter based State Machine Implementation

10.4. A Loadable Counter based Micro Program FSM

10.5. Counter based Micro Program FSM with Conditional Branching

10.6. Register Based Controller

10.7. Micro program State Machine with Subroutine Support

10.8. Micro program State Machine with Nested Loop Support

10.9. Design Example of a Wavelet Processor

10.10. References

11. Micro Programmed based Adaptive Filtering Applications

11.1. Introduction

11.2. Adaptive Filters Configurations

11.3. Adaptive Algorithms

11.4. Channel Equalizer using NLMS

11.5. Echo Canceller

11.6. Micro Coded State Machine based Design for Adaptive Algorithm

11.7. Architecture of LEC Micro coded Accelerator

11.8. Exercise

11.9. References

12. Exploring Design Options for CORDIC based DDFS Architectures

12.1. Introduction

12.2. Direct Digital Frequency Synthesizer

12.3. Design of a Basic DDFS

12.4. CORDIC Algorithm

12.5. HW Mapping of Modified CORDIC Algorithm

12.6. Exercise

12.7. References

13. Digital Design of Communication Systems

13.1. Top level Design Options

13.2. Digital Communication System

13.3. Source Encoding

13.4. Encryption

13.5. Channel Coding

13.6. Digital Baseband Modulation

13.7. Exercise

13.8. References

Extra informatie: 
Hardback
606 pagina's
Januari 2011
1168 gram
252 x 177 x 37 mm
Wiley-Blackwell us

Levertijd: 5 tot 11 werkdagen