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K. C. Chang

Digital Systems Design with VHDL and Synthesis

An Integrated Approach

€ 153.95

K.C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.


Taal / Language : English

Inhoudsopgave:
Introduction
1(3)
Integrated Design Process and Methodology
1(1)
Book Overview
2(2)
VHDL and Digital Circuit Primitives
4(28)
Flip Flop
4(11)
Latch
15(3)
Three-State Buffer
18(4)
Combinational Gates
22(4)
VHDL Synthesis Rules
26(4)
Pads
30(1)
Exercises
30(2)
VHDL Simulation and Synthesis Environment and Design Process
32(21)
Synopsys VHDL Simulation Environment Overview
32(4)
Mentor Quick VHDL Simulation Environment
36(3)
Synthesis Environment
39(6)
Synthesis Technology Library
45(2)
VHDL Design Process for a Block
47(5)
Exercises
52(1)
Basic Combinational Circuits
53(38)
Selector
53(15)
Encoder
68(3)
Code Converter
71(2)
Equality Checker
73(6)
Comparator with Single Output
79(3)
Comparator with Multiple Outputs
82(7)
Exercises
89(2)
Basic Binary Arithmetic Circuits
91(52)
Half Adder and Full Adder
91(6)
Carry Ripple Adder
97(4)
Carry Look Ahead Adder
101(18)
Countone Circuit
119(4)
Leading Zero Circuit
123(9)
Barrel Shifter
132(5)
Exercises
137(6)
Basic Sequential Circuits
143(44)
Signal Manipulator
143(7)
Counter
150(16)
Shift Register
166(11)
Parallel to Serial Converter
177(3)
Serial to Parallel Converter
180(6)
Exercises
186(1)
Registers
187(35)
General Framework for Designing Registers
187(2)
Interrupt Registers
189(4)
DMA and Control Registers
193(3)
Configuration Registers
196(5)
Reading Registers
201(1)
Register Block Partitioning and Synthesis
202(11)
Testing Registers
213(6)
Microprocessor Registers
219(2)
Exercises
221(1)
Clock and Reset Circuits
222(29)
Clock Buffer and Clock Tree
222(3)
Clock Tree Generation
225(3)
Reset Circuitry
228(2)
Clock Skew and Fixes
230(8)
Synchronization between Clock Domains
238(4)
Clock Divider
242(4)
Gated Clock
246(4)
Exercises
250(1)
Dual-Port RAM, FIFO, and DRAM Modeling
251(37)
Dual-Port RAM
251(9)
Synchronous FIFO
260(6)
Asynchronous FIFO
266(8)
Dynamic Random Access Memory (DRAM)
274(12)
Exercises
286(2)
A Design Case Study: Finite Impulse Response Filter Asic Design
288(53)
Design Description
288(5)
Design Partition
293(14)
Design Verification
307(15)
Design Synthesis
322(3)
Worst-Case Timing Analysis
325(4)
Best-Case Timing Analysis
329(2)
Netlist Generation
331(3)
Postlayout Verification
334(3)
Design Management
337(2)
Exercises
339(2)
A Design Case Study: A Microprogram Controller Design
341(49)
Microprogram Controller
341(3)
Design Description and Partition
344(18)
Design Verification
362(15)
Design Synthesis
377(5)
Postsynthesis Timing Verification
382(1)
Preparing Release Functional Vectors
383(4)
Postlayout Verification
387(1)
Design Management
387(2)
Exercises
389(1)
Error Detection and Correction
390(18)
Error Detection and Correction Code
390(1)
Single Error Detecting Codes
390(1)
Single Error Correcting Codes
391(2)
Single Error Correcting and Double Error Detecting Codes
393(1)
Error Detecting and Correcting Code Design Example
394(6)
Design Verification
400(3)
Design Synthesis
403(4)
Netlist Generation and FPGA Place and Route
407(1)
Exercises
407(1)
Fixed-Point Multiplication
408(37)
Multiplication Concept
408(1)
Unsigned Binary Multiplier
409(10)
2`s Complement Multiplication
419(4)
Wallace Tree Adders
423(2)
Booth-Wallace Tree Multiplier
425(4)
Booth-Wallace Tree Multiplier Verification
429(2)
Booth-Wallace Tree Multiplier Synthesis
431(6)
Multiplication with Shift and Add
437(5)
Exercises
442(2)
References
444(1)
Fixed-Point Division
445(22)
Basic Division Concept
445(6)
32-Bit Divider
451(1)
Design Partition
452(1)
Design Optimization
453(5)
Design Verification
458(4)
Design Synthesis
462(3)
Exercises
465(1)
Reference
466(1)
Floating-Point Arithmetic
467(18)
Floating-Point Number Representation
467(1)
Floating-Point Addition
468(11)
Floating-Point Multiplication
479(5)
Exercises
484(1)
Appendix A Package Pack 485(11)
Index 496
Extra informatie: 
Hardback
518 pagina's
Januari 1999
1089 gram
273 x 191 x 32 mm
Wiley-Blackwell us

Levertijd: 5 tot 11 werkdagen